Joao Baptista Dos Santos Martins

Produção Bibliográfica

    2016 (Total: 2)
  • ISSN A influência de programas de capacitação na construção da identidade profissional: O caso do CI-Brasile da Microeletrônica (Acta Scientiarum. Human and Social Sciences)
  • doi ISSN An Improved Solution for Node Location Multilateration Algorithms in Wireless Sensor Networks (ELECTRONICS LETTERS)
    2015 (Total: 1)
  • ISSN System-Level Design of a Reconfigurable CT SD Modulator for Multi-Standard Wireless Application (JICS. Journal of Integrated Circuits and Systems (Ed. Português))
    2012 (Total: 1)
  • doi ISSN Design of power efficient butterflies from Radix-2 DIT FFT using adder compressors with a new XOR gate topology (Analog Integrated Circuits and Signal Processing (Dordrecht. Online))
    2011 (Total: 1)
  • doi ISSN Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation (International Journal of Reconfigurable Computing (Print))
    2008 (Total: 2)
  • doi ISSN Current mode instrumentation amplifier with rail-to-rail input and output (Analog Integrated Circuits and Signal Processing)
  • doi ISSN Design of na Integrated Low Power High CMRR Instrumentation Amplifier for Biomedical Applications (Analog Integrated Circuits and Signal Processing)
    2019 (Total: 1)
  • Development of a Hardened 150nm Standard Cell Library (Radiation Effects on Integrated Circuits and Systems for Space Application)
    2010 (Total: 1)
  • Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation)
    2007 (Total: 1)
  • A Comparison of Layout Implementations of Pipelined And Non-Pipelined Signed Radix-4 Array Multiplier And Modified Booth Multiplier Architectures (VLSI-SoC: From System to Silicon (no prelo))
    2001 (Total: 1)
  • Estimativa de Capacitâncias e Consumo de Potência em Circuitos Combinacionais CMOS no Nível Lógico (III Escola de Microeletrônica)
    2001 (Total: 1)
  • III Escola de Microeletrônica da SBC-Sul
    2020 (Total: 1)
  • Multi-Bit-Upset Memory Using New Error Correction Code Methodology (11TH IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS)
    2019 (Total: 2)
  • Behavioral Modeling of a Control Module for an Energy-investing Piezoelectric Harvester (SBCCI2019 - Symposium on Integrated Circuits and Systems Design)
  • doi Smart Water Management System using the Microcontroller ZR16S08 as IoT Solution (10th IEEE Latin American Symposium on Circuits and Systems)
    2018 (Total: 1)
  • doi Semi-Autonomous Navigation for Virtual Tactical Simulations in the Military Domain (8th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH 2018))
    2016 (Total: 1)
  • Design considerations for Radiation Hardened ASIC used as tecnological payload in NANOSATC-BR1 (II Latin American IAA CubeSat Workshop)
    2015 (Total: 1)
  • System-level Design of single-bit Sigma-Delta modulators based on MSA and SNR Data Graphics (28th Symposium on Integrated Circuits and Systems Design)
    2014 (Total: 2)
  • High Level Design of A CT SD Modulator for Multi-Standard Applications (XXIX South Symposium on Microelectronics - SIM 2014)
  • System-Level Design of a Reconfigurable CT SD Modulator for Multi-Standard Wireless Applications (27th Symposium on Integrated Circuits and Systems Design - SBCCI '14)
    2013 (Total: 3)
  • A Hybrid Method to Detectting Failures in Mobile Sensor Networks Using Localization Algorithms (11th IEEE INTERNATIONAL NEWCAS CONFERENCE)
  • A Reconfigurable Decimation Filter Design for a Cascade 2-2 Sigma-Delta Analog-to-Digital Converter (IBERCHIP XIX Workshop)
  • Interactive Power and Area Reduction Applied to an UHF RFID Digital Block (Workshop on Circuits and Systems, WCAS)
    2012 (Total: 5)
  • 14-bit DR, 20 kHz BW, 2-2 MASH SI-Sigma Delta Modulator Using Low-Distortion Feedforward Topology (2012 IEEE International Symposium on Circuits and Systems (ISCAS))
  • An approach to localization scheme of wireless sensor networks based on artificial neural networks and Genetic Algorithms (2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS))
  • doi Genetic Algorithms and Simulated Annealing optimization methods in wireless sensor networks localization using artificial neural networks (2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS))
  • doi High-order low-distortion switched-current cascade 2?2?2 ΣΔ modulator (2012 IEEE Third Latin American Symposium on Circuits and Systems (LASCAS))
  • Mobility Support Enhancements for a Wireless Sensor Network Framework (27th South Symposium on Microelectronics)
    2011 (Total: 6)
  • doi Design of pipelined butterflies from Radix-2 FFT with Decimation in Time algorithm using efficient adder compressors (Circuits and Systems (LASCAS), 2011 IEEE Second Latin American Symposium on)
  • Hardware Implementation of a Centroid-based Localization Algorithm for Mobile Sensor Networks (IEEE International Symposium on Circuits and Systems (ISCAS))
  • Iterative Mode Hardware Implementation of CORDIC Algorithm (26th South Symposium on Microelectronics)
  • Iterative Mode Hardware Implementation of the Add One Carry Select Adder (26th South Symposium on Microelectronics)
  • Review of Localization Schemes Using Artificial Neural Networks in Wireless Sensor Networks (26th South Symposium on Microelectronics)
  • Simple Power and Electromagnetic Analyses: evaluation of protected RSA hardware implementations (6th International Conference on Security and Cryptography)
    2010 (Total: 6)
  • A Comparison between Hardware and Software Full Duplex Internet Protocol Version 4 Implementations (XVI Iberchip Workshop, 2010)
  • A Full Duplex Implementation of Internet Protocol Version 4 in an FPGA Device (VI SOUTHERN PROGRAMMABLE LOGIC CONFERENCE)
  • An Efficient Implementation of Montgomery Powering Ladder in Reconfigurable Hardware (23rd Symposium on Integrated Circuits and Systems Design)
  • Architectural Exploration in the Butterflies of the Radix-2 Decimation in Time FFT Algorithm (XVI Iberchip Workshop, 2010)
  • CentroidM: a Centroid-based Localization Algorithm for Mobile Sensor Networks (Symposium on Integrated Circuits and Systems Design)
  • Montgomery Modular Multiplication on Reconfigurable Hardware: Fully Systolic Array vs Parallel Implementation (VI Southern Programmable Logic Conference)
    2009 (Total: 5)
  • A FPGA based Network stack with a reduced number of layers (SBCCI - SBMICRO - SFORUM)
  • A Gigabit UDP/IP Network Stack in FPGA (ICECS 2009 - IEEE International Conference on Electronics Circuits and Systems)
  • An UDP/IP Network Stack in FPGA (SBCCI - SBMICRO - SFORUM)
  • Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates (19th International Workshop on Power and Timing Modeling Optimization and Simulation)
  • Implementation Flow of a Full Duplex Internet Protocol Hardware Core According to the Brazil-IP Program Methodology (24th South Symposium on Microlectronics)
    2008 (Total: 1)
  • A VLSI Architecture Suitable for Mid-Level Image Processing (4th Southern Conference on Programmable Logic)
    2007 (Total: 3)
  • An Area Cost Optimized Fast Parallel Label Assignment VLSI Architecture (IEEE SPL2007 - III Southern Conference on Programmable Logic)
  • Currente Mode Instrumentation Amplifier with Rail-to-Rail Input and Output (20 th Symposium on Integrated Circuits and Systems Design)
  • Design of na Integrated Low Power High CMRR Instrumentation Amplifier for Biomedical Applications (20 th Symposium on Integrated Circuits and Systems Design)
    2006 (Total: 6)
  • COMPARAÇÃO ENTRE OS CODECS DE COMPRESSÃO DE VOZ iLBC E G.729 CONSIDERANDO ATRASO E PONTUAÇÃO MOS (XIV Jornadas de Jovens Pesquisadores da AUGM)
  • Development and Verification of a Real Time Clock ASIC (VIII MICROELECTRONIC SCHOOL)
  • GERADOR DE ARRITMIAS CARDÍACAS (XIV Jornadas de Jovens Pesquisadores da AUGM)
  • SISTEMA DE MARCA-PASSO CARDÍACO COM MONITORAMENTO E CONTROLE BLUETOOTH (XX Congresso Brasileiro de Engenharia Biomédica - Instrumentação Biomédica)
  • VHDL Control System for Linear Ultrasonic Motors (13th Symposium of Smart Strucutres and Materials)
  • VHDL High Resolution Control System for Linear Motor Ultrassonic (VII CONFERÊNCIA INTERNACIONAL DE APLICAÇÕES INDUSTRIAIS)
    2005 (Total: 7)
  • A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier (IFIP VLSI SoC 2005 - International Conference on Very Large Scale Integration of Systems-on-Chip)
  • A Low-Price Platform to Test Digital Integrated Circuits Using FPGA (48th IEEE International Midwest Symposium on Circuits & Systems)
  • A Methodology for Estimation of Capacitance and Power in Combinational CMOS Complex Gates (IFIP VLSI SoC 2005 - International Conference on Very Large Scale Integration of Systems-on-Chip)
  • Estimativa de Capacitância e Consumo de Potência de Portas Lógicas Complexas ao Nível Lógico (XI Workshop IBERCHIP (IWS 2005))
  • Implementation of an Access Control System Using Reconfigurable Architecture (20th South Symposium on Microelectronis)
  • New Methodology in the Power Estimation in CMOS Combinational Circuits (48th IEEE International Midwest Symposium on Circuits & Systems)
  • Position Controller for Linear Ultrasonic Motors (20th South Symposium on Microelectronis)
    2004 (Total: 7)
  • An Entire Design Flow for Automated Integrated Circuits Synthesis in Mentor Graphics Environment (19th South Symposium on Microelectronis)
  • Array Hybrid Multiplier versus Modified Booth Multiplier: Comparing Area and Power Consumption of Layout Implementations of Signed Radix-4 Architectures (2004 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004))
  • Capacitance Estimation and Power Consumption in CMOS Complex gate at Logic-Level (19th South Symposium on Microelectronis)
  • Controle Digital de um Marcapasso Cardíaco com Saída para Visualização do Sinal Através de Interface de Comunicação Serial (X Workshop Iberchip (IWS 2004))
  • Fluxo de Projeto Completo para Síntese Automática de Circuitos Integrados no Ambiente Mentor Graphics. (X Workshop Iberchip (IWS 2004))
  • Implementação de uma Arquitetura para um Divisor Combinacional de 16 Bits em Complemento de 2. (X Workshop Iberchip (IWS 2004))
  • VHDL Description and Simulation of a High Resolution Control System for Linear Ultrasonic Motors (USE 2004 - Symposium on Ultrasonic Electronics)
    2003 (Total: 5)
  • Comparing 2s Complement Multipliers With Binary and Hybrid Operand Encoding (18th South Symposium on Microelectronics)
  • FPGA Implementation of a VVI Temporary Pacemaker Digital Control (IFIP VLSI SoC 2003 - International Conference on Very Large Scale Integration of Systems-on-Chip)
  • Low Power High-CMRR CMOS Instrumentation Amplifier for Biomedical Applications (18th South Symposium on Microelectronics)
  • Low-Power High-CMRR CMOS (IFIP VLSI SoC 2003 - International Conference on Very Large Scale Integration of Systems-on-Chip)
  • Módulo Integrado de Controle de um Marcapasso Cardíaco de Demanda Externo (IX Workshop Iberchip)
    2002 (Total: 2)
  • Estimativa de Capacitâncias e Potência em Circuitos CMOS (VIII Workshop Internacional Iberchip)
  • Microwind2: A CAD tool for CMOS Circuits Design (17 th South Symposium on Microelectronics)
    2001 (Total: 1)
  • Interconnection Length Estimation at Logic Level (Symposium on Integrated Circuits and Systems Design)
    2000 (Total: 4)
  • Accurate Modeling of Capacitance and Power in Logic Level Circuits (International Workshop on Logic Synthesis 2000)
  • Capacitance and Power Modeling at Logic Level (International Conference on Chip Design Automation)
  • Estimação de Capacitâncias e Potência de Circuitos CMOS ao Nível Lógico (VI Workshop IBERCHIP)
  • Power Estimation at Logic Level Considering Interconnection Capacitances (XV International Conference on Microelectronics and Packaging)
    1999 (Total: 1)
  • Capacitance Estimation in CMOS Logic Gates (XIV Microeletronics Seminar)
    1998 (Total: 1)
  • Techniques for Power Estimation in VLSI Circuits (XIII UFRGS MICROELECTRONICS SEMINAR)
    2014 (Total: 1)
  • Using the NANOSATC-BR1 for evaluation of the effects caused by space radiation incidence on a radiation hardened by design ASIC (1st IAA Latin American CubeSat Workshop)
    2009 (Total: 2)
  • IMPLEMENTAÇÃO DO PROTOCOLO INTERNET VERSÃO QUATRO EM HARDWARE (24ª Jornada Acadêmica Integrada da UFSM)
  • PROJETO GLT - GERENCIADOR DE LIGAÇÕES TELEFÔNICAS (24ª Jornada Acadêmica Integrada da UFSM)

Produção Técnica

    2018 (Total: 1)
  • Development of a Hardened 150nm Standard Cell Library
    2017 (Total: 1)
  • Development of a Hardened 150nm Standard Cell Library
    2016 (Total: 1)
  • Development of a Hardened 150nm Standard Cell Library
    2015 (Total: 1)
  • Development of a Hardened 150nm Standard Cell Library
    2002 (Total: 1)
  • Estimativa de Capacitâncias e Potência em Circuitos CMOS
    2001 (Total: 1)
  • Interconnection Length Estimation at Logic Level
    2014 (Total: 2)
  • Microcontroladores, o caso da Santa Maria Design House
  • ZR16 - Microcontrolador Genuinamente do Brasil
    2018 (Total: 2)
  • Circuito Integrado - ZR16LP08
  • Circuito Integrado - ZR16S08
    2007 (Total: 1)
  • Metodologia de Localização de Regiões Candidatas em Sistemas de Reconhecimento Automático de Caracteres - Numero de registro provisório da Patente junto ao INPI-0000270607032603
    2018 (Total: 1)
  • Metodologia de Localização de Regiões Candidatas em Sistemas de Reconhecimento Automático de Caracteres
    2005 (Total: 1)
  • PROJETO DE CONSULTORIA, ASSESSORIA E EXTENSÃO NA ÁREA DE CIRCUITOS DIGITAIS
    2005 (Total: 1)
  • Projeto de Consultoria, Assessoria e Extensão na Área de Computação
    2006 (Total: 1)
  • Revisor de periódico 'Revista Ciências Exatas'

Produção Artística

Não informado

Orientações Concluídas

    2020 (Total: 1)
  • CÓDIGO CORRETOR DE ERROS MULTI BIT UPSET COM DUPLA VERIFICAÇÃO
    2018 (Total: 2)
  • Análise de Desempenho de Algoritmos de Roteamento de Nodos em Uma Rede de Sensores Sem Fio Aplicada a Cidades Inteligentes
  • Implementação do Protocolo de Comunicação DTN Aplicado para Cidades Inteligentes
    2017 (Total: 1)
  • UMA PROPOSTA DE UM COMPILADOR LLVM PARA O ZR16LP
    2016 (Total: 2)
  • ESTUDO DE TOPOLOGIAS DE CIRCUITOS ELETRÔNICOS APLICADOS À ENERGY HARVESTING DE CAMPOS ELETROMAGNÉTICOS
  • OTIMIZAÇÃO DO MÉTODO DE LOCALIZAÇÃO DE MONTE CARLO PARA REDES DE SENSORES SEM FIO MÓVEIS
    2015 (Total: 1)
  • Identificação do Comportamento do Pastejo em Ruminantes através do Uso de Filtros Digitais Baseados em Análise Espectral
    2014 (Total: 1)
  • Método de Multilateração para Algoritmos de Localização em Redes de Sensores Sem Fio
    2013 (Total: 3)
  • Algoritmo de Localização Utilizando o Método MMSE para Cálculo de Posição de Nós Sensores em uma rede Móvel
  • Contra Medida por Randomização de Acesso à Memória em Arquitetura de Criptografia de Chave Pública
  • Minimização do Cabeçalho do Protocolo de Comunicação IPV6 Visando a Melhoria de Desempenho em Redes Locais
    2012 (Total: 3)
  • Localização de Nodos em Redes de Sensores Sem Fio Utilizando Redes Neurais Artificiais e Metaheurísticas
  • Método Híbrido de Detecção de Defeitos em Redes de Sensores Móveis Utilizando Algoritmo de Localização
  • MODULADOR SI-ΣΔ CASCATA 2-2 EMPREGANDO ARQUITETURA DE BAIXA DISTORÇÃO APLICADO À CONVERSÃO AD
    2011 (Total: 1)
  • Arquiteturas de Criptografia de Chave Pública: Análise de Desempenho e Robustez
    2010 (Total: 2)
  • Exploração de Operadores Aritméticos na Transformada Rápida de Fourier
  • IMPLEMENTAÇÃO DE ARQUITETURAS DE PILHA UDP/IP EM HARDWARE RECONFIGURÁVEL BASEADO NO DESEMPENHO DE VAZÃO, LATÊNCIA E TAXA DE PERDA DE QUADROS
    2009 (Total: 2)
  • IMPLEMENTAÇÃO E OTIMIZAÇÃO DE UMA ARQUITETURA DE REVERBERAÇÃO DIGITAL EMPREGANDO TÉCNICAS DE PROCESSAMENTO MULTITAXA SOBRE PLATAFORMA RECONFIGURÁVEL
  • UMA NOVA ARQUITETURA DE PILHA DE COMUNICAÇÃO EM REDE COM UM NÚMERO REDUZIDO DE CAMADAS
    2008 (Total: 1)
  • Extração de reconhecimento de caracteres ópticos a partir do co-projeto de hardware e software sobre plataforma reconfigurável
    2007 (Total: 1)
  • NOVA METODOLOGIA DE LOCALIZAÇÃO DE REGIÕES CANDIDATAS EM IMAGENS DIGITAIS UTILIZANDO ARQUITETURAS RECONFIGURÁVEIS
    2005 (Total: 2)
  • Nova Metodologia para a Estimativa de Capacitância e Consumo de Potência de Portas Lógicas Complexas CMOS no Nível Lógico
  • PROTOTIPAÇÃO E ANÁLISE DE CIRCUITOS MULTIPLICADORES ARRAY DE BAIXO CONSUMO
    2004 (Total: 1)
  • Módulo Integrado para Controle Digital de Marca-Passo Temporário
    2004 (Total: 1)
  • Estágio Supervisionado em Engenharia Elétrica TSM Antenas
    2016 (Total: 1)
  • VERIFICAÇÃO DE IDENTIDADE PROFISSIONAL UTILIZANDO ANÁLISE EXPLORATÓRIA DE DADOS E A ANÁLISE ESTRUTURADA DE REDES: O CASO DO CI-BRASIL E DA MICROELETRÔNICA NO CNPq
    2009 (Total: 1)
  • ALGORITMO DE LOCALIZAÇÃO DE NODOS PARA REDES DE SENSORES MÓVEIS
    2006 (Total: 1)
  • Projeto PCI-Estudo, Análise e Geração de um ASIC Dedicado
    2004 (Total: 1)
  • Desenvolvimento de Uma Biblioteca de CAD para Estimativa de Capacitâncias Parasitas de Circuitos CMOS no Nível Lógico