doi ISSN Modeling and Predicting Noise-Induced Failure Rates in Ultra-Low-Voltage SRAM Bitcells Affected by Process Variations (IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS)

doi ISSN Random Telegraph Noise in Analog CMOS Circuits (IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS)

doi ISSN Random Telegraph Noise Modeling for Circuit Analysis: RTN in Ring Oscillators (IEEE Journal of the Electron Devices Society)

doi ISSN A Compact Statistical Model for the Low-Frequency Noise in Halo-Implanted MOSFETs: Large RTN Induced by Halo Implants (IEEE TRANSACTIONS ON ELECTRON DEVICES)

doi ISSN A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping (IEEE TRANSACTIONS ON ELECTRON DEVICES)

doi ISSN Autocorrelation Analysis as a Technique to Study Physical Mechanisms of MOSFET Low-Frequency Noise (IEEE TRANSACTIONS ON ELECTRON DEVICES)

doi ISSN A Physics-Based Statistical RTN Model for the Low Frequency Noise in MOSFETs (IEEE TRANSACTIONS ON ELECTRON DEVICES)

doi An Overview on Statistical Modeling of Random Telegraph Noise in the Frequency Domain (Noise in Nanoscale Semiconductor Devices)

doi Towards Unifying the Statistical Modeling of Charge Trapping in Time and Frequency Domain (2021 IEEE Latin America Electron Devices Conference (LAEDC))

doi Unified Compact Modeling of Charge Trapping in 1/f Noise, RTN and BTI (2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM))

Variability-based Analysis Technique Revealing Physical Mechanisms of MOSFET Low-frequency Noise (International Conference on Microelectronic Test Structures. 2017 (ICMTS))

doi A physics-based RTN variability model for MOSFETs (2014 IEEE International Electron Devices Meeting (IEDM))

doi On-chip circuit for massively parallel BTI characterization (2011 IEEE International Integrated Reliability Workshop (IIRW))

doi Modeling the impact of RTS on the reliability of ring oscillators (Symposium on Integrated Circuits and System Design)

doi NBTI-aware technique for transistor sizing of high-performance CMOS gates (LATW 2009)

Modeling the Impact of NBTI on the Reliability of Arithmetic Circuits (8th Microelectronics Students Forum - Chip in the Pampa)

Numerical Method for Modeling Process Variations and NBTI. In: IEEE Insternational Conference on Very Large Scale Integration (VLSI-SOC 2008)

Amplificador de Transcondutância Operacional Auto-Oscilante (39ª Jornada Acadêmica Integrada da UFSM)

ESTRATÉGIAS LOW POWER EM CIRCUITOS DIGITAIS: APLICAÇÕES PRÁTICAS EM UM FREQUENCY LOCKED LOOP (39ª Jornada Acadêmica Integrada da UFSM)

COMPARADOR STRONGARM: CARACTERÍSTICAS DE OPERAÇÃO E METODOLOGIA DE PROJETO (38ª Jornada Acadêmica Integrada)

Geração de Clock para Aplicações em IOT Utilizando um Frequency-Locked-Loop (38ª Jornada Acadêmica Integrada)

PROJETO DE UM CONTROLE ASSÍNCRONO PARA UM CONVERSOR A/D DO TIPO SAR (38ª Jornada Acadêmica Integrada)

MÉTODO NUMÉRICO PARA A MODELAGEM DE VARIAÇÕES DE PROCESSO E NBTI (XX Salão de Iniciação Científica)

O IMPACTO DO NBTI NA CONFIABILIDADE DE CIRCUITOS ARITMÉTICOS (XX Salão de Iniciação Científica)

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Projeto de comparadores strongarm com calibração de offset