doi ISSN Design Space Exploration of DVFS on On-Chip Hybrid Communication Networks (JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS))

doi ISSN Energy-aware fully-adaptive resource provisioning in collaborative CPU-FPGA cloud environments (JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING)

doi ISSN Multiprovision: a Design Space Exploration tool for multi-tenant resource provisioning in CPU-GPU environments (DESIGN AUTOMATION FOR EMBEDDED SYSTEMS)

doi ISSN MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems (INTEGRATION-THE VLSI JOURNAL)

doi ISSN An energy efficient multi-target binary translator for instruction and data level parallelism exploitation (DESIGN AUTOMATION FOR EMBEDDED SYSTEMS)

doi ISSN ERIN: Energy-Aware Resource Provisioning Framework for CPU-FPGA Multi-tenant Environment (IEEE Design & Test)

doi ISSN Resource-Aware Collaborative Allocation for CPU-FPGA Cloud Environments (IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS)

doi ISSN Synergistically Exploiting CNN Pruning and HLS Versioning for Adaptive Inference on Multi-FPGAs at the Edge (ACM Transactions on Embedded Computing Systems)

doi ISSN Dynamic concurrency throttling on NUMA systems and data migration impacts (DESIGN AUTOMATION FOR EMBEDDED SYSTEMS)

doi ISSN Data clustering for efficient approximate computing (DESIGN AUTOMATION FOR EMBEDDED SYSTEMS (DORDRECHT. ONLINE))

ISSN An Adaptive and Dynamic Reconfigurable Multiprocessor System to Improve Software Productivity (IET Computers & Digital Techniques (Print))

doi ISSN A transparent and adaptive reconfigurable system (Microprocessors and Microsystems)

ISSN Mixing static and dynamic strategies for high performance and low area reconfigurable systems (International Journal of High Performance Systems Architecture (Print))

ISSN Towards a Multiple-ISA Embedded System (Journal of Systems Architecture)

doi ISSN Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment (International Journal of Reconfigurable Computing (Print))

ISSN Measuring the Efficiency of Cache Memory on Java Processors for Embedded Systems (JICS. Journal of Integrated Circuits and Systems)

doi SIS-ASTROS: An Integrated Simulation Environment for the Artillery Saturation Rocket System (ASTROS) (Lecture Notes in Networks and Systems)

Processador ARM e System-on-Chips para Sistemas Embarcados (Tópicos em Micro e Nano Eletrônica)

Heterogeneous Behavior of Applications and Systems (Adaptable Embedded Systems)

Multicore Platforms: Processors, Communications and Memories (Adaptable Embedded Systems)

ERA ? Embedded Reconfigurable Architectures (Reconfigurable Computing: From FPGAs to Hardware/Software Codesign)

Multi-Core System on Chip (Handbook of Signal Processing Systems)

An Automatic Framework for Collaborative CPU Thread Throttling and FPGA HLS-Versioning (XIV Symposium on Computing Systems Engineering)

Enhancing Collaboration Between 3D Artists and Programmers in Game Development with Agile Practices (Simposio Brasileiro de Jogos e Entretenimento Digital (SBGAMES))

Exploiting Virtual Layers and Pruning for FPGA-Based Adaptive Traffic Classification (27th Euromicro Conference on Digital System Design (DSD))

Exploration Tool for Collaborative Provisioning and DVFS in Heterogeneous Cloud Environments (XIV Symposium on Computing Systems Engineering)

TARA: Enhancing Real-Time Network Traffic Classification with Hardware Virtual Layers (37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI))

Adaptive Inference on Reconfigurable SmartNICs for Traffic Classification (IEEE International Conference on Advanced Information Networking and Applications)

Design Space Exploration for CNN Offloading to FPGAs at the Edge (IEEE Computer Society Annual Symposium on VLSI)

Dynamic Offloading Decisions for Improved Performance and Energy Efficiency in Heterogeneous IoT-Edge-Cloud Continuum (IEEE Computer Society Annual Symposium on VLSI)

Pruning and Early-Exit Co-Optimization for CNN Acceleration on FPGAs (Design Automation and Test in Europe)

Resource Provisioning for CPU-FPGA Environments with Adaptive HLS-Versioning and DVFS (IEEE Computer Society Annual Symposium on VLSI)

ADAFLOW: A Framework for Adaptive Dataflow CNN Acceleration on FPGAs (Design Automation and Test in Europe)

ConfAx: Exploiting Approximate Computing for Configurable FPGA CNN Acceleration at the Edge (IEEE International Symposium on Circuits and Systems (ISCAS))

On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments (35ᵗʰ Symposium on Integrated Circuits and Systems Design)

SIS-ASTROS: An Integrated Simulation System for the Artillery Saturation Rocket System (ASTROS) (International Conference on Simulation and Modeling Methodologies, Technologies and Applications)

A Framework for Collaborative Allocation in CPU-FPGA Multi-tenant Environments (34th Symposium on Integrated Circuits and Systems Design (SBCCI))

ETCF - Energy-Aware CPU Thread Throttling and Workload Balancing Framework for CPU-FPGA Collaborative Environments (Brazilian Symposium on Computing Systems Engineering (SBESC))

ETCG: Energy-Aware CPU Thread Throttling for CPU-GPU Collaborative Environments (34th Symposium on Integrated Circuits and Systems Design (SBCCI))

Exploiting HLS-Generated Multi-Version Kernels to ImproveCPU-FPGA Cloud Systems (26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021))

FAIR: Fully-Adaptive Framework for Improving Resource Provisioning in Collaborative CPU-FPGA Cloud Environments (International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD))

TRIPP: Transparent Resource Provisioning for Multi-Tenant CPU-GPU based Cloud Environments (XI Brazilian Symposium on Computing Systems Engineering)

A Management Technique for Concurrent Access toa Reconfigurable Accelerator (33rd Symposium on Integrated Circuits and Systems Design (SBCCI 2020))

Maximizing Throughput-per-Joule of a Hybrid Communication Infrastructure Through a Software- Hardware based DVFS Mechanism (33rd Symposium on Integrated Circuits and Systems Design (SBCCI 2020))

MCEA: A Resource-Aware Multicore CGRA Architecture forthe Edge (30th International Conference on Field Programmable Logic and Applications (FPL 2020))

Unlocking the Full Potential of Heterogeneous Accelerators by Using a Hybrid Multi-Target Binary Translator (33rd Symposium on Integrated Circuits and Systems Design (SBCCI 2020))

A Runtime Power-Aware Phase Predictor for CGRAs (International Conference on Reconfigurable Computing and FPGAs (ReConFig))

Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection (Design, Automation and Test in Europe (DATE))

Power-Aware Phase Oriented Reconfigurable Architecture (IEEE International Conference on Electronics Circuits and Systems (ICECS))

DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability (14th International Symposium on Applied Reconfigurable Computing)

Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture (14th International Symposium on Applied Reconfigurable Computing)

HyHeMPS: A Hybrid Communication Infrastructure for MPSoC (Brazilian Symposium on Computing Systems Engineering)

Improving Software Productivity and Performance through a Transparent SIMD Execution (Symposium on Integrated Circuits and Systems Design)

Runtime Vectorization of Conditional Code and Dynamic Range Loops to ARM NEON Engine (Brazilian Symposium on Computing Systems Engineering)

Semi-Autonomous Navigation For Virtual Tactical Simulations In the Military Domain (International Conference on Simulation and Modeling Methodologies, Technologies and Applications)

A Framework to Automatically Generate Heterogeneous Organization Reconfigurable Multiprocessing (IEEE International Symposium on Circuits and Systems (ISCAS))

Improving EDP in Multi-Core Embedded Systems through Multidimensional Frequency Scaling (IEEE International Symposium on Circuits and Systems (ISCAS))

A Reconfigurable Heterogeneous Multicore with a Homogeneous ISA (Design, Automation and Test in Europe (DATE))

Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous System (International Symposium on Applied Reconfigurable Computing (ARC))

The Impact of Heterogeneity on a Reconfigurable Multicore System (IEEE Computer Society Annual Symposium on VLSI)

Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks (Symposium in Applied Reconfigurable Computing)

Towards a Dynamic and Reconfigurable Multicore Heterogeneous System (IV Simpósio Brasileiro de Engenharia de Sistemas Computacionais)

A Run-Time Adaptive Multiprocessor System (The IEEE International Symposium on Circuits and System)

A transparent and energy aware reconfigurable multiprocessor platform for efficient ILP and TLP exploitation (Design, Automation and Test Conference in Europe (DATE))

Simultaneous Reconfiguration of Issue-width and Instruction Cache for a VLIW Processor (International Conference on Embedded Computer Systems: Architectures, Modelind and Simulation)

A Dynamically Reconfigurable Architecture with a Two-Level Binary Translation Mechanism (5th Workshop on Reconfigurable Computing)

A Reconfigurable Fabric Supporting Full C/C++ Input (International Workshop on Reconfigurable Communication-centric Systems-on-Chip)

A Transparent and Adaptable Multiple-ISA Embedded System (Engineering of Reconfigurable Systems and Algorithms)

Towards an Adaptable Multiple-ISA Reconfigurable Processor (International Symposium on Applied Reconfigurable Computing)

A Low-Energy Approach for Context Memory in Reconfigurable Systems (IEEE International Parallel And Distributed Processing Symposium (IPDPS) - Reconfigurable Architectures Workshop (RAW), 2010)

Decreasing the Impact of the Context Memory on Reconfigurable Architectures (HiPEAC Workshop on Reconfigurable Computing)

Floating point unit implementation for a reconfigurable architecture (South Symposium on Microelectronics)

Implementação de uma Unidade de Ponto Flutuante para uma Arquitetura Reconfigurável. (XVI IBERCHIP Workshop)

TLP and ILP exploitation through Reconfigurable Multiprocessing System (IEEE International Parallel And Distributed Processing Symposium (IPDPS) - Reconfigurable Architectures Workshop (RAW))

A Low Cost and Adaptable Routing Network for Reconfigurable Systems (IEEE International Parallel And Distributed Processing Symposium (IPDPS) - Reconfigurable Architectures Workshop (RAW), 2009,)

Dynamically Adapted Low Power ASIPs (International Workshop on Reconfigurable Computing, 2009)

Balancing Rconfigurable Data Path Resources According to Applications Requirements (15th Reconfigurable Architecture Workshop)

Binary Translation Process to Optimize Nanowire Arrays Usage (IEEE International Symposium on Circuits and Systems)

Reducing Interconnection Cost in Coarse-Grained Dynamic Computing through Multistage Network (International Conference on Field Programmable Logic and Applications)

Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems (International Workshop on Applied Reconfigurable Computing)

Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications (Design, Automation and Test in Europe)

Transparent Dataflow Execution for Embedded Applications (IEEE Computer Society Annual Symposium on VLSI)

Advantages of Java Processors in Cache Performance and Power for Embedded Applications (Embedded Computer Systems: Architectures, MOdeling, and Simulation)

Cache performance impacts for Stack Machines in Embedded Systems (SBCCI)

CReAMS: An Embedded Multiprocessor Platform (International Symposium on Applied Reconfigurable Computing)

17° Escola de Microeletrônica/30° Simpósio Sul de Microeletrônica

Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection

Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks

A transparent and energy aware reconfigurable multiprocessor platform for efficient ILP and TLP exploitation

TLP and ILP exploitation through Reconfigurable Multiprocessing System

Transparent Dataflow Execution for Embedded Applications

HyHeMPS: A Hybrid Communication Infrastructure for MPSoC

Runtime Vectorization of Conditional Code and Dynamic Range Loops to ARM NEON Engine

A Framework to Automatically Generate Heterogeneous Organization Reconfigurable Multiprocessing

The Impact of Heterogeneity on a Reconfigurable Multicore System

A Two-Level Binary Translation Mechanism

CReAMS: An Embedded System Platform

Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems

CBT da Viatura de Comando e Controle do Sistema ASTROS MK6

Revisor de periódico 'DESIGN AUTOMATION FOR EMBEDDED SYSTEMS'

Revisor de periódico 'IEEE Design & Test'

Revisor de periódico 'THE JOURNAL OF SUPERCOMPUTING (DORDRECHT. ONLINE)'

Revisor de periódico 'DESIGN AUTOMATION FOR EMBEDDED SYSTEMS'

Revisor de periódico 'IEEE Design & Test'

Revisor de periódico 'THE JOURNAL OF SUPERCOMPUTING (DORDRECHT. ONLINE)'

Collaborative-Aware CPU Thread Throttling and FPGA HLS-Versioning

Exploiting Virtual Layers and Reconfigurability for FPGA Convolutional Neural Network Accelerators

Maximizing Throughput-per-Joule of a Hybrid Communication Infrastructure Through a Software-Hardware based DVFS Mechanism

Mitigando o Impacto Da Comunicação no Consumo de Energia e Área em Chip Pela Utilização De Uma Infraestrutura De Comunicação Híbrida em Sistemas Multiprocessados

Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection

Um Framework para Geração Automática de Sistemas Multiprocessados Reconfiguráveis Heterogêneos

Resource Provisioning Framework for CPU-FPGA Environments with Adaptive and Synergistic HLS-Versioning and DVFS

OTIMIZAÇÃO DO MAKESPAN E DE ENERGIA: UMA ANÁLISE EXPLORATÓRIA SOBRE O IMPACTO DAS POLÍTICAS DE ESCALONAMENTO E DE DVFS EM ARQUITETURAS CPU-GPU NA NUVEM

PROJETO DE UM SCANNER 3D DE BAIXO CUSTO DEDICADO AO SOFTWARE BLENDER 3D

DESIGN SPACE EXPLORATION OF HYBRID TOPOLOGIES ANDDVFS IN ON-CHIP COMMUNICATION NETWORKS

EXPLORAÇÃO DE MÚLTIPLOS ALGORITMOS DE ESCALONAMENTODE NÚCLEOS OPENCL PARA SISTEMAS DE PROCESSAMENTO EMNUVEM MULTI-INQUILINO BASEADOS EM CPUS E GPUS

"Exploração Mútua de Paralelismo em Nível de Dados e Instruções Através de Aceleradores Transparentes Baseados em Tradução Binária

ESTUDO DO IMPACTO DA UTILIZAÇÃO DE CROSSBAR COMO INFRAESTRUTURA DE COMUNICAÇÃO EM SISTEMAS MULTIPROCESSADOS Santa Maria, RS 2018

ESTUDO DO IMPACTO DO AGRUPAMENTO DE STREAMING PROCESSORS EM CLUSTERS NO DESEMPENHO DE APLICAÇÕES NA ARQUITETURA FERMI

DESENVOLVIMENTO DE UM ALGORITMO DE DISTRIBUIÇÃO DE TAREFAS PARA UM MPSOC DE INFRAESTRUTURA DE COMUNICAÇÃO HÍBRIDA

ESTUDO DO IMPACTO DE DIFERENTES ARBITRAGENS DE BARRAMENTO EM SISTEMAS MULTIPROCESSADOS

Exploração da técnica de reconfiguração parcial em um sistema reconfigurável de grão grosso

Estudo do Impacto da Implementação de um Escalonador em uma Arquitetura Multiprocessada com Núcleos Heterogêneos

Dynamic and Static Task Mapping to a Network-on-Chip Using Machine Learning Techniques

Estudo do Impacto da Implementação de um Escalonador em uma Arquitetura Multiprocessada com Núcleos Heterogêneos

Modelagem e Desenvolvimento de um Sistema de Monitoramento Remoto de Sinais Vitais Humanos

Uso de Steering Behavior para Simulação de Manobras Militares

Acoplamento e Validação Funcional do Sistema Reconfigurável DIM

Estudo do impacto do Mapeamento de Aplicações do Domínio Embarcado em um Sistema Multiprocessado Reconfigurável baseado em NoC

Evaluation of Heterogeneous CReAMS

Explorando a União entre Memória de Contextos e de Instruções de uma Arquitetura Reconfigurável Visando a Redução de Área e Consumo de Potência em Sistemas Embarcados

Exploração da Heterogeneidade de ILP para a Redução do Consumo de Energia e Área de um Ambiente Multiprocessado Embarcado