Mateus Beck Rutzig

Produção Bibliográfica

    2021 (Total: 1)
  • doi ISSN Resource-Aware Collaborative Allocation for CPU-FPGA Cloud Environments (IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS)
    2020 (Total: 1)
  • doi ISSN Dynamic concurrency throttling on NUMA systems and data migration impacts (DESIGN AUTOMATION FOR EMBEDDED SYSTEMS)
    2019 (Total: 1)
  • doi ISSN Data clustering for efficient approximate computing (DESIGN AUTOMATION FOR EMBEDDED SYSTEMS (DORDRECHT. ONLINE))
    2015 (Total: 1)
  • ISSN An Adaptive and Dynamic Reconfigurable Multiprocessor System to Improve Software Productivity (IET Computers & Digital Techniques (Print))
    2014 (Total: 1)
  • doi ISSN A transparent and adaptive reconfigurable system (Microprocessors and Microsystems)
    2012 (Total: 2)
  • ISSN Mixing static and dynamic strategies for high performance and low area reconfigurable systems (International Journal of High Performance Systems Architecture (Print))
  • ISSN Towards a Multiple-ISA Embedded System (Journal of Systems Architecture)
    2011 (Total: 1)
  • doi ISSN Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment (International Journal of Reconfigurable Computing (Print))
    2007 (Total: 1)
  • ISSN Measuring the Efficiency of Cache Memory on Java Processors for Embedded Systems (JICS. Journal of Integrated Circuits and Systems)
    2014 (Total: 1)
  • Processador ARM e System-on-Chips para Sistemas Embarcados (Tópicos em Micro e Nano Eletrônica)
    2012 (Total: 2)
  • Heterogeneous Behavior of Applications and Systems (Adaptable Embedded Systems)
  • Multicore Platforms: Processors, Communications and Memories (Adaptable Embedded Systems)
    2011 (Total: 1)
  • ERA ? Embedded Reconfigurable Architectures (Reconfigurable Computing: From FPGAs to Hardware/Software Codesign)
    2010 (Total: 1)
  • Multi-Core System on Chip (Handbook of Signal Processing Systems)
    2021 (Total: 1)
  • Exploiting HLS-Generated Multi-Version Kernels to ImproveCPU-FPGA Cloud Systems (26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021))
    2020 (Total: 4)
  • A Management Technique for Concurrent Access toa Reconfigurable Accelerator (33rd Symposium on Integrated Circuits and Systems Design (SBCCI 2020))
  • Maximizing Throughput-per-Joule of a Hybrid Communication Infrastructure Through a Software- Hardware based DVFS Mechanism (33rd Symposium on Integrated Circuits and Systems Design (SBCCI 2020))
  • MCEA: A Resource-Aware Multicore CGRA Architecture forthe Edge (30th International Conference on Field Programmable Logic and Applications (FPL 2020))
  • Unlocking the Full Potential of Heterogeneous Accelerators by Using a Hybrid Multi-Target Binary Translator (33rd Symposium on Integrated Circuits and Systems Design (SBCCI 2020))
    2019 (Total: 3)
  • A Runtime Power-Aware Phase Predictor for CGRAs (International Conference on Reconfigurable Computing and FPGAs (ReConFig))
  • Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection (Design, Automation and Test in Europe (DATE))
  • Power-Aware Phase Oriented Reconfigurable Architecture (IEEE International Conference on Electronics Circuits and Systems (ICECS))
    2018 (Total: 6)
  • DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability (14th International Symposium on Applied Reconfigurable Computing)
  • Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture (14th International Symposium on Applied Reconfigurable Computing)
  • HyHeMPS: A Hybrid Communication Infrastructure for MPSoC (Brazilian Symposium on Computing Systems Engineering)
  • Improving Software Productivity and Performance through a Transparent SIMD Execution (Symposium on Integrated Circuits and Systems Design)
  • Runtime Vectorization of Conditional Code and Dynamic Range Loops to ARM NEON Engine (Brazilian Symposium on Computing Systems Engineering)
  • Semi-Autonomous Navigation For Virtual Tactical Simulations In the Military Domain (International Conference on Simulation and Modeling Methodologies, Technologies and Applications)
    2017 (Total: 2)
  • A Framework to Automatically Generate Heterogeneous Organization Reconfigurable Multiprocessing (IEEE International Symposium on Circuits and Systems (ISCAS))
  • Improving EDP in Multi-Core Embedded Systems through Multidimensional Frequency Scaling (IEEE International Symposium on Circuits and Systems (ISCAS))
    2016 (Total: 3)
  • A Reconfigurable Heterogeneous Multicore with a Homogeneous ISA (Design, Automation and Test in Europe (DATE))
  • Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous System (International Symposium on Applied Reconfigurable Computing (ARC))
  • The Impact of Heterogeneity on a Reconfigurable Multicore System (IEEE Computer Society Annual Symposium on VLSI)
    2015 (Total: 1)
  • Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks (Symposium in Applied Reconfigurable Computing)
    2014 (Total: 1)
  • Towards a Dynamic and Reconfigurable Multicore Heterogeneous System (IV Simpósio Brasileiro de Engenharia de Sistemas Computacionais)
    2013 (Total: 2)
  • A Run-Time Adaptive Multiprocessor System (The IEEE International Symposium on Circuits and System)
  • A transparent and energy aware reconfigurable multiprocessor platform for efficient ILP and TLP exploitation (Design, Automation and Test Conference in Europe (DATE))
    2012 (Total: 1)
  • Simultaneous Reconfiguration of Issue-width and Instruction Cache for a VLIW Processor (International Conference on Embedded Computer Systems: Architectures, Modelind and Simulation)
    2011 (Total: 4)
  • A Dynamically Reconfigurable Architecture with a Two-Level Binary Translation Mechanism (5th Workshop on Reconfigurable Computing)
  • A Reconfigurable Fabric Supporting Full C/C++ Input (International Workshop on Reconfigurable Communication-centric Systems-on-Chip)
  • A Transparent and Adaptable Multiple-ISA Embedded System (Engineering of Reconfigurable Systems and Algorithms)
  • Towards an Adaptable Multiple-ISA Reconfigurable Processor (International Symposium on Applied Reconfigurable Computing)
    2010 (Total: 5)
  • A Low-Energy Approach for Context Memory in Reconfigurable Systems (IEEE International Parallel And Distributed Processing Symposium (IPDPS) - Reconfigurable Architectures Workshop (RAW), 2010)
  • Decreasing the Impact of the Context Memory on Reconfigurable Architectures (HiPEAC Workshop on Reconfigurable Computing)
  • Floating point unit implementation for a reconfigurable architecture (South Symposium on Microelectronics)
  • Implementação de uma Unidade de Ponto Flutuante para uma Arquitetura Reconfigurável. (XVI IBERCHIP Workshop)
  • TLP and ILP exploitation through Reconfigurable Multiprocessing System (IEEE International Parallel And Distributed Processing Symposium (IPDPS) - Reconfigurable Architectures Workshop (RAW))
    2009 (Total: 2)
  • A Low Cost and Adaptable Routing Network for Reconfigurable Systems (IEEE International Parallel And Distributed Processing Symposium (IPDPS) - Reconfigurable Architectures Workshop (RAW), 2009,)
  • Dynamically Adapted Low Power ASIPs (International Workshop on Reconfigurable Computing, 2009)
    2008 (Total: 5)
  • Balancing Rconfigurable Data Path Resources According to Applications Requirements (15th Reconfigurable Architecture Workshop)
  • Binary Translation Process to Optimize Nanowire Arrays Usage (IEEE International Symposium on Circuits and Systems)
  • Reducing Interconnection Cost in Coarse-Grained Dynamic Computing through Multistage Network (International Conference on Field Programmable Logic and Applications)
  • Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems (International Workshop on Applied Reconfigurable Computing)
  • Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications (Design, Automation and Test in Europe)
    2007 (Total: 1)
  • Transparent Dataflow Execution for Embedded Applications (IEEE Computer Society Annual Symposium on VLSI)
    2006 (Total: 2)
  • Advantages of Java Processors in Cache Performance and Power for Embedded Applications (Embedded Computer Systems: Architectures, MOdeling, and Simulation)
  • Cache performance impacts for Stack Machines in Embedded Systems (SBCCI)
    2011 (Total: 1)
  • CReAMS: An Embedded Multiprocessor Platform (International Symposium on Applied Reconfigurable Computing)

Produção Técnica

    2015 (Total: 1)
  • 17° Escola de Microeletrônica/30° Simpósio Sul de Microeletrônica
    2019 (Total: 1)
  • Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection
    2015 (Total: 1)
  • Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks
    2013 (Total: 1)
  • A transparent and energy aware reconfigurable multiprocessor platform for efficient ILP and TLP exploitation
    2010 (Total: 1)
  • TLP and ILP exploitation through Reconfigurable Multiprocessing System
    2007 (Total: 1)
  • Transparent Dataflow Execution for Embedded Applications
    2018 (Total: 2)
  • HyHeMPS: A Hybrid Communication Infrastructure for MPSoC
  • Runtime Vectorization of Conditional Code and Dynamic Range Loops to ARM NEON Engine
    2017 (Total: 1)
  • A Framework to Automatically Generate Heterogeneous Organization Reconfigurable Multiprocessing
    2016 (Total: 1)
  • The Impact of Heterogeneity on a Reconfigurable Multicore System
    2011 (Total: 2)
  • A Two-Level Binary Translation Mechanism
  • CReAMS: An Embedded System Platform
    2008 (Total: 1)
  • Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems

Produção Artística

Não informado

Orientações Concluídas

    2020 (Total: 1)
  • Maximizing Throughput-per-Joule of a Hybrid Communication Infrastructure Through a Software-Hardware based DVFS Mechanism
    2018 (Total: 1)
  • Mitigando o Impacto Da Comunicação no Consumo de Energia e Área em Chip Pela Utilização De Uma Infraestrutura De Comunicação Híbrida em Sistemas Multiprocessados
    2017 (Total: 1)
  • Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection
    2014 (Total: 1)
  • Um Framework para Geração Automática de Sistemas Multiprocessados Reconfiguráveis Heterogêneos
    2015 (Total: 4)
  • Dynamic and Static Task Mapping to a Network-on-Chip Using Machine Learning Techniques
  • Estudo do Impacto da Implementação de um Escalonador em uma Arquitetura Multiprocessada com Núcleos Heterogêneos
  • Modelagem e Desenvolvimento de um Sistema de Monitoramento Remoto de Sinais Vitais Humanos
  • Uso de Steering Behavior para Simulação de Manobras Militares
    2014 (Total: 4)
  • Acoplamento e Validação Funcional do Sistema Reconfigurável DIM
  • Estudo do impacto do Mapeamento de Aplicações do Domínio Embarcado em um Sistema Multiprocessado Reconfigurável baseado em NoC
  • Evaluation of Heterogeneous CReAMS
  • Explorando a União entre Memória de Contextos e de Instruções de uma Arquitetura Reconfigurável Visando a Redução de Área e Consumo de Potência em Sistemas Embarcados
    2011 (Total: 1)
  • Exploração da Heterogeneidade de ILP para a Redução do Consumo de Energia e Área de um Ambiente Multiprocessado Embarcado