Leonardo Londero De Oliveira

Produção Bibliográfica

    2022 (Total: 1)
  • doi ISSN Mobile Localization Techniques for Wireless Sensor Networks: Survey and Recommendations (ACM Transactions on Sensor Networks)
    2021 (Total: 1)
  • doi ISSN Dedicated Shapelet Distance Engine for Time-Series Classification (IEEE Design & Test)
    2016 (Total: 1)
  • doi ISSN An Improved Solution for Node Location Multilateration Algorithms in Wireless Sensor Networks (ELECTRONICS LETTERS (ONLINE))
    2007 (Total: 1)
  • doi A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures (Vlsi-Soc: From Systems To Silicon)
    2018 (Total: 1)
  • Localização de Nodos em Redes de Sensores Móveis: Princípios e Aplicação em Hardware
    2022 (Total: 1)
  • Comparative Analysis of Hardware Implementations of a Convolutional Neural Network (35ᵗʰ Symposium on Integrated Circuits and Systems Design)
    2020 (Total: 3)
  • doi Hardware Accelerator for Shapelet Distance Computation in Time-Series Classification (2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI))
  • doi Lightweight Cryptographic Instruction Set Extension on Xtensa Processor (2020 IEEE International Symposium on Circuits and Systems (ISCAS))
  • doi Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication (2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI))
    2019 (Total: 2)
  • doi Exploring the Training and Execution Acceleration of a Neural Network in a Reconfigurable General-purpose Processor for Embedded Systems (2019 17th IEEE International New Circuits and Systems Conference (NEWCAS))
  • doi GCoL - A General Co-simulator Applied to Wireless Sensor Networks and RTL Design (2019 17th IEEE International New Circuits and Systems Conference (NEWCAS))
    2018 (Total: 3)
  • doi An Efficient Single Core Flexible Processor Architecture for 4096-bit Montgomery Modular Multiplication and Exponentiation (2018 IEEE International Symposium on Circuits and Systems (ISCAS))
  • doi Exploring Asynchronous End-to-End Communication Through a Synchronous NoC (2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI))
  • doi Exploring RSA Performance up to 4096-bit for Fast Security Processing on a Flexible Instruction Set Architecture Processor (2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS))
    2013 (Total: 1)
  • doi A Hybrid Method to Detecting Failures in Mobile Sensor Networks Using Localization Algorithms (NEWCAS)
    2012 (Total: 2)
  • doi An Approach to Localization Scheme of Wireless Sensor Networks Based on Artificial Neural Networks and Genetic Algorithms (NEWCAS)
  • doi Genetic Algorithms and Simulated Annealing Optimization Methods in Wireless Sensor Networks Localization Using Artificial Neural Networks (MWSCAS)
    2011 (Total: 4)
  • A Reconfigurable ASIC Implementation of a Network Gateway Based on the IPv4 Protocol (Workshop on Circuits and Systems Design)
  • doi Hardware Implementation of a Centroid-based Localization Algorithm for Mobile Sensor Networks (IEEE International Symposium on Circuits and Systems (ISCAS))
  • Iterative Mode Hardware Implementation of CORDIC Algorithm (South Symposium on Microelectronics)
  • Review of Localization Schemes Using Artificial Neural Networks in Wireless Sensor Networks (South Symposium on Microelectronics)
    2010 (Total: 1)
  • doi CentroidM: a Centroid-based Localization Algorithm for Mobile Sensor Networks (Symposium on Integrated Circuits and Systems Design)
    2005 (Total: 4)
  • A Comparison of Layout Implementations of Pipelined And Non-Pipelined Signed Radix-4 Array Multiplier And Modified Booth Multiplier Architectures (IFIP VLSI-SOC 2005)
  • doi A Low-Price Platform to Test Digital Integrated Circuits Using FPGA (48th IEEE MWSCAS International Midwest Symposium on Circuits and Systems)
  • doi A new methodology in power estimation in CMOS combinational circuits at logic level ()
  • Implementation of an Access Control System Using Reconfigurable Architecture (XX SIM - Simpósio Sul de Microeletrônica)
    2004 (Total: 3)
  • An Entire Design Flow for Automated Integrated Circuits Synthesis in Mentor Graphics Environment (XIX Simpósio Sul de Microeletrônica)
  • doi Array hybrid multiplier versus modified booth multiplier: comparing area and power consumption of layout implementations of signed radix-4 architectures (The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.)
  • Controle Digital de um Marcapaso Cardíaco com Saída para Visualização do Sinal através de Interface de Comunicação Serial (IBERCHIP?04)
    2003 (Total: 1)
  • Comparing 2's Complement Multipliers With Binary and Hybrid Operand Encoding (XVIII SIM - Simpósio Sul de Microeletrônica)
    2002 (Total: 1)
  • Amplificador Operacional CMOS de Baixa Potência para Implementação de em Marca-passo Cardíaco (XVII CONGRESSO REGIONAL DE INICIAÇÃO CIENTÍFICA E TECNOLÓGICA)
    2001 (Total: 2)
  • A 5V-Bits CMOS Paralell ADC Based on Lookup Table Encoding (I Fórum de Estudantes de Microeletrônica)
  • Conversor A/D FLASH de 5 bits (XVI Congresso Regional de Iniciação Científica e Tecnológica - CRICTE)
    2000 (Total: 2)
  • Biblioteca de Células Digitais para o Projeto de Circuitos Integrados (XV Congresso Regional de Iniciação Científica e Tecnológica - CRICTE)
  • Projetos de Circuitos Integrados Utilizando a Ferramenta Magic/Linux (XV Congresso Regional de Iniciação Científica e Tecnológica - CRICTE)
    2011 (Total: 3)
  • Estudo de um framework de simulação para Redes de Sensores Sem Fio (Jornada Acadêmica Integrada)
  • Estudo de um Simulador para Rede de Sensores (Jornada Acadêmica Integrada)
  • Revisão acerca de algoritmos de localização para redes de sensores móveis (Jornada Acadêmica Integrada)
    2010 (Total: 1)
  • Algoritmo de Localização de Nodos para Redes de Sensores Móveis (Jornada Acadêmica Integrada)

Produção Técnica

    2018 (Total: 1)
  • IEEE CASS Santa Maria Workshop
    2015 (Total: 1)
  • XVII Escola de Microeletrônica Sul (EMICRO 2015) e XXX Simpósio Sul de Microeletrônica (SIM 2015)
    2001 (Total: 1)
  • III Escola de Microeletrônica da SBC Sul
    2022 (Total: 1)
  • Revisor de periódico 'Ad Hoc Networks'
    2021 (Total: 1)
  • Revisor de periódico 'Ad Hoc Networks'
    2020 (Total: 1)
  • Revisor de periódico 'Ad Hoc Networks'
    2019 (Total: 1)
  • Revisor de periódico 'Ad Hoc Networks'
    2018 (Total: 1)
  • Revisor de periódico 'Ad Hoc Networks'
    2017 (Total: 1)
  • Revisor de periódico 'Ad Hoc Networks'

Produção Artística

Não informado

Orientações Concluídas

    2018 (Total: 2)
  • ACELERAÇÃO DO TREINAMENTO E EXECUÇÃO DE UMA REDE NEURAL EM UM PROCESSADOR DE PROPÓSITO GERAL RECONFIGURÁVEL PARA SISTEMAS EMBARCADOS
  • IMPLEMENTAÇÃO DE UMA REDE NEURAL ARTIFICIAL EM HARDWARE PARA DETECÇÃO E CORREÇÃO DE RUÍDOS EM IMAGENS
    2016 (Total: 1)
  • DESCRIÇÃO E PROJETO EM HDL DE UMA REDE NEURAL PERCEPTRON: RECONHECIMENTO DE CARACTERES EM BITMAP